1. Field of the Invention
This invention relates generally to techniques for fabricating closely spaced structures, such as, for example, features in an integrated circuit.
2. Description of the Related Art
Techniques for forming closely spaced structures have many applications. For example, integrated circuits are continuously being reduced in size. The sizes of the constituent features that form the integrated circuits, e.g., electrical devices and interconnect lines, are also constantly being decreased to facilitate this size reduction.
The trend of decreasing feature size is evident, for example, in memory circuits or devices such as dynamic random access memories (DRAMs), flash memory, static random access memories (SRAMs), ferroelectric (FE) memories, etc. To take one example, DRAM typically includes millions of identical circuit elements, known as memory cells. A memory cell typically consists of two electrical devices: a storage capacitor and an access field effect transistor. Each memory cell is an addressable location that may store one bit (binary digit) of data. A bit may be written to a cell through the transistor and may be read by sensing charge in the capacitor. Some memory technologies employ elements that can act as both a storage device and a switch (e.g., dendritic memory employing silver-doped chalcogenide glass) and some nonvolatile memories do not require switches for each cell (e.g., magnetoresistive RAM) or incorporate switches into the memory element (e.g., EEPROM for flash memory).
In another example, flash memory typically includes millions of flash memory cells containing floating gate field effect transistors that may retain a charge. The presence or absence of a charge in the floating gate determines the logic state of the memory cell. A bit may be written to a cell by injecting charge to or removing charge from a cell. Flash memory cells may be connected in different architecture configurations, each with different schemes for reading bits. In a “NOR” architecture configuration, each memory cell is coupled to a bit line and may be read individually. In a “NAND” architecture configuration, memory cells are aligned in a “string” of cells, and an entire bit line is activated to access data in one of the string of cells.
In general, by decreasing the sizes of the electrical devices that constitute a memory cell and the sizes of the conducting lines that access the memory cells, the memory devices may be made smaller. Additionally, storage capacities may be increased by fitting more memory cells on a given area in the memory devices. The need for reductions in feature sizes, however, is more generally applicable to integrated circuits, including general purpose and specialty processors.
The continual reduction in feature sizes places ever greater demands on the techniques used to form the features. For example, photolithography is commonly used to pattern these features. Typically, photolithography involves passing light through a reticle and focusing the light onto a photochemically-active photoresist material. As a result, the ultimate resolution of lithography techniques is limited by factors such as optics and light or radiation wavelength.
In conjunction with radiation of a particular wavelength, photolithography utilizes photoresist compatible with that radiation. After being developed, the photoresist acts as a mask to transfer a pattern to an underlying material. The photoresist is sufficiently robust to withstand the development step without deforming and is also sufficiently robust to withstand an etch for transferring the mask pattern to an underlying material. As feature sizes decrease, however, the widths of the photoresist mask features also decrease, but typically without a corresponding decrease in the heights of these mask features. Due to the high aspect ratio of these mask features, it may be difficult to maintain the structural integrity of these thin mask features during the development and pattern transfer steps. Thus, the availability of sufficiently robust photoresist materials can limit the ability of photolithography to print features, as those features continue to decrease in size.
Accordingly, there is a continuing need for high resolution methods to pattern features.